The world is going digital. Cell phone communications are an example of digital signal communications, and satellite broadcasts are typically digital. Many wired telephone connections are still analog, as are most television broadcasts, but it not inconceivable that these medium will also move towards digital, and analog signals for communication will largely be a thing of the past.
In parallel with the “digital revolution”, the world is going wireless. Cell phones are an example of wireless communication.
The whole field of digital communications has spawned several areas of specialty and expertise, including error detection and correction techniques, to name a few.
“Coding” is a term that often shows up in any discussion of digital signal processing. Generally, coding may refer to converting an analog signal (such as a movie image) into a digital format (ones and zeroes). Thus, for example, a motion picture which is originally on film (an analog format) can be converted to a data file (digital format) such as by “MPEG” encoding. When it is desired to view the MPEG-encoded film (and it should be understood that our eyes respond to analog images), the data file must be “de-coded”, returned to its original analog format.
“Coding” may also refer to taking a digital signal which is already in one digital format, and changing it to another digital format so as to be suitable for a particular purpose, such as storage or transmission over a given medium. For example, an original CD wave file can be trans-coded (or compressed) to another format, such as MP3, resulting in a smaller data file (for example 3 MByte rather than 30 MByte).
Error Detection and Correction
Generally, “error detection” is the ability to detect errors that are made due to noise or other impairments in the course of the transmission from the transmitter to the receiver, and “error correction” is the ability to correct errors at the receiver.
Data being sent (transmitted), whether over a wired connection or a wireless connection, is typically arranged into packets or blocks having a prescribed size, and an error correction code is often generated and sent along with the packet or block. At the receiving end, the received data can be compared against the error correction code to determine whether the data contained within the packet became corrupted. In some cases, using forward error correction (FEC), the corrupted data can be corrected. In other cases, the receiving station can signal the transmitting station that corrupt data was received, with a request to re-transmit the data. (In yet other cases, corrupted data may simply be ignored.)
Error-correcting codes can be divided into block codes and convolutional codes. Other block error-correcting codes, such as Reed-Solomon codes transform a chunk of bits into a (longer) chunk of bits in such a way that errors up to some threshold in each block can be detected and corrected. However, in practice errors often occur in bursts rather than at random. This is often compensated for by shuffling (interleaving) the bits in the message after coding. Then any burst of bit-errors is broken up into a set of scattered single-bit errors when the bits of the message are unshuffled (de-interleaved) before being decoded.
One feature of an error correction scheme may be to organize data in such a way that errors, as are to be expected, can successfully be dealt with. Interleaving is a way of arranging data in such a way that error correction schemes can successfully be applied to corrupt data to recover the original data from corrupted data.
Interleaving
Interleaving involves re-arranging data in a non-contiguous way in order to increase performance. Interleaving is mainly used in data communication, multimedia file formats, radio transmission (for example in satellites) or by ADSL (asymmetrical digital subscriber link). Historically, interleaving has also been used in ordering block storage on hard disks. The term “multiplexing” is sometimes used to refer to the interleaving of digital signal data.
Today, interleaving is mainly used in digital data transmission technology, to protect the transmission against “burst errors”. Burst errors overwrite (corrupt, alter) several bits in a row, but seldom occur. Interleaving is used to address/solve this problem.
All data is transmitted with some control bits (independently from the interleaving), such as error correction bits, that enable the channel decoder to correct a certain number of altered bits. If a burst error occurs, and more than this number of bits is altered, the codeword cannot be correctly decoded. So the bits of a number of codewords are “interleaved” and then transmitted. That way, a burst error affects only a correctable number of bits in each codeword, so the decoder can decode the codewords correctly.
For example, an error correcting code is applied so that a channel codeword has four bits and one-bit errors can be corrected. The channel codewords are put into a block like this: aaaabbbbccccddddeeeeffffgggg (the block comprises seven 4-bit codewords: a, b, c, d, e and f)
Transmitted without interleaving, the received signal should be (error-free transmission):                aaaabbbbccccddddeeeeffffgggg        
However, a burst error could corrupt a number of contiguous bits of the transmitted data so that the received signal looks like this:                aaaabbbbccc_deeeeffffgggg        
In this example, the codeword “cccc” is altered in one bit (the fourth c is missing), and can be corrected. However, the codeword “dddd” is altered in three bits (the first three d's are missing). It is possible that it cannot be decoded (decoding failure) or might be decoded into a wrong codeword (false decoding). Which of the two happens depends on the error correcting code applied.
Burst error, by definition, typically corrupts a sequence of bits, as in the previous example, which may completely wipe out a particular codeword, or at least corrupt sufficient bits of the codeword that it cannot be corrected.
Interleaving, generally, requires re-arranging the bits of the codewords—spreading them out, so to speak—so that anticipated burst errors can be corrected.
Consider the following example, wherein the first of the four bits of each of the seven codewords (a1,b1,c1,d1,e1,f1,g1) are transmitted, then the second bits of each of the seven codewords (a2,b2,c2,d2,e2,f2,g2) are transmitted, then the seven third bits (a3,b3,c3,d3,e3,f3,g3), then the seven fourth bits (a4,b4,c4,d4,e4,f4,g4). This is called “interleaving”. (At the receiving end, the interleaved/re-arranged bits must be put back into their original order—this is called “de-interleaving”).
The transmitted signal (with interleaving) should look like (error-free transmission):                abcdefgabcdefgabcdefgabcdefg        
(More detailed, the transmission looks like this: a1,b1,c1,d1,e1,f1,g1, a2,b2,c2,d2,e2,f2,g2, a3,b3,c3,d3,e3,f3,g3, a4,b4,c4,d4,e4,f4,g4)
However, a burst error could corrupt the data so that the signal looks like this:                abcdefgabcd_bcdefgabcdefg        
Here, as in the previous example, four contiguous bits are missing, in this case the second e, f, and g bits (e2,f2,g2), and the third a bit (a3).
And, the de-interleaved transmission with the above burst error would look like this:                aa_abbbbccccdddde_eef_ffg_gg        
In each of the codewords aaaa, eeee, ffff, gggg only one bit is altered, so a one-bit-error-correcting-code can decode everything correctly.
Of course, all this interleaving requires computational overhead, and that is the general topic of the present invention—namely, techniques related to interleaving and de-interleaving.
Convolutional Interleavers
A convolutional interleaver generally consists of a set of shift registers, each with a fixed delay. In a typical convolutional interleaver, the delays are nonnegative integer multiples of a fixed integer (although a general multiplexed interleaver allows arbitrary delay values). Each new symbol from the input signal feeds into the next shift register and the oldest symbol in that register becomes part of the output signal.
Convolutional interleavers and de-interleavers are commonly employed in a FEC scheme to protect against a burst of errors from being sent to a block decoder, such as a Reed-Solomon decoder. It is well known that interleaving techniques improve error correction capability.
FIG. 1 is a simplified schematic block diagram illustrating a typical convolutional interleaver and deinterleaver, according to the prior art. In many applications, interleaved data are buffered using static random access memory (SRAM). The width of data to be stored into the memory matches the interleaver/deinterleaver symbol size. For the interleaver 100, each successive branch (102, 103, . . . , 109) has J more symbols than the immediately preceding branch. For example, branch 103 has J more symbols than branch 102.
To the contrary, for the deinterleaver 120, each successive branch (102′, 103′, 104′, . . . , 109′) has J fewer symbols than the immediately preceding branch. For example, branch 103′ has J fewer symbols than branch 102′. Unless indicated otherwise, “I” represents the interleaving depth and “J” represents the interleaving increment. Thus, one branch has a different delay from another branch. The foregoing characteristic, i.e., the delay difference, thus creates sequential-write addresses and non-sequential-read addresses, or vice versa, when conventional memory access is used. This asymmetry between write and read addresses affects data throughput. Furthermore, another problem associated with SRAM is that SRAM is relatively more expensive than other types of memory, such as, synchronous dynamic random access memory (SDRAM).
In some applications, SDRAM is used to store interleaved data. However, use of SDRAM based on the interleaving/deinterleaving approach described above also has its disadvantages. For example, one disadvantage is that by using conventional SDRAM access, the overhead ACTIVE and PRECHARGE command cycles for non-sequential read or write addresses significantly reduce data throughput. Another disadvantage is that when conventional SDRAM is used, some applications may not have enough bandwidth to satisfy the requirement that the data width associated with the memory needs to be equal to the symbol size.
Data Communications Systems
FIG. 2 depicts a typical prior art communication system including a transmitter 210 for converting an input data sequence TX into an outgoing analog signal V1 transmitted through a communication channel 214 to a receiver 212. Receiver 212 converts signal V2 back into an output data sequence RX matching the transmitters' incoming data sequence TX. Since channel 214 can introduce random noise into signal V2, it is possible that some of the bits of the RX sequence will not match corresponding bits of the TX sequence. To reduce the likelihood that noise in channel 214 will produce errors in the RX sequence, transmitter 210 includes a forward error correction (FEC) encoder 216, such as for example a Reed-Solomon encoder, for encoding the incoming data sequence TX into a sequence A of N-byte words. Each word of sequence A “over-represents” a corresponding portion of the TX sequence because it contains redundant data. A convolutional interleaver 218 interleaves bytes of successive words of word sequence A to produce an output word sequence B supplied to a modulator 220. Modulator 220 generates signal V1 to represent successive bytes of word sequence B.
A demodulator 222 within receiver 212 demodulates signal V2 to produce a word sequence B′. Word sequence B′ will nominally match the word sequence B input to the transmitter's modulator 220, though some of the bytes forming word sequence B′ may include bit errors caused by noise in channel 214. A deinterleaver circuit 224 deinterleaves word sequence B′ to produce a word sequence A′ nominally matching word sequence A, although it too may include errors resulting from the errors in word sequence B′. An FEC decoder 226 then decodes word sequence A′ to produce the output data sequence RX.
Although the A′ sequence may contain some errors, it is possible for FEC decoder 226 to produce an outgoing sequence RX matching the TX sequence because words of the A′ sequence contain redundant data. When a portion of an A′ sequence word representing any particular portion of the RX data is corrupted due to an error in the B′ sequence, another redundant portion of the A′ sequence word also representing that particular portion of the RX sequence may not be corrupted. FEC decoder 226 is able to determine which portions of each A′ sequence word are not corrupted and uses the uncorrupted portions of those words as a basis for determining bit values of its corresponding portion the RX sequence. Each possible FEC scheme will have a limited capability for correcting byte errors. For example, a (255, 16) Reed-Solomon code, including 16 bytes of redundant data to form a 255 bytes code word can correct up to 8 byte errors, but no more.
It is possible for some portion of the RX sequence to contain an error when there are excessive errors within an A′ sequence word representing that particular portion of the RX sequence, but interleaver 218 and deinterleaver 224 help to reduce the chances of that happening. Since noise in channel 14 can occur in bursts that may persist long enough to corrupt portions of signal V1 conveying every byte of a B′ sequence word, interleaver 218 improves the system's noise immunity by interleaving bytes of successive words of sequence A to produce word sequence B. Since each word of sequence A produced by FEC encoder 216 contains redundant data describing a particular section of the TX sequence, interleaving the words of sequence A to produce words of sequence B has the effect of spreading out information conveyed by signal V1 so that a single noise burst in channel 214 is less likely to corrupt an excessive number of bytes of information representing the same portion of the TX sequence.
FIG. 3 is another diagram of a communications system comprising a convolutional interleaver. The ITU Forward Error Correction (FEC) definition is composed of four processing layers, as illustrated in FIG. 3. There are no dependencies on input data protocol in any of the FEC layers. FEC synchronization is fully internal and transparent. Any data sequence will be delivered from the encoder input to decoder output.
The FEC section uses various types of error correcting algorithms and interleaving techniques to transport data reliably over the cable channel.                Reed-Solomon (RS) Coding—Provides block encoding and decoding to correct up to three symbols within an RS block.        Interleaving—Evenly disperses the symbols, protecting against a burst of symbol errors from being sent to the RS decoder.        Randomization—Randomizes the data on the channel to allow effective QAM demodulator synchronization.        Trellis Coding—Provides convolutional encoding and with the possibility of using soft decision trellis decoding of random channel errors.        
With regard to interleaving, interleaving is included in the modem between the RS block coding and the randomizer to enable the correction of burst noise induced errors. In both 64-QAM and 256-QAM a convolutional interleaver is employed.
Convolutional interleaving is illustrated in FIG. B.8 of the ITU document. At the start of an FEC frame defined in a subsequent subclause, the interleaving commutator position is initialized to the top-most branch and increments at the RS symbol frequency, with a single symbol output from each position. With a convolutional interleaver, the RS code symbols are sequentially shifted into the bank of I registers (the width of each register is 7 bits which matches the RS symbol size). Each successive register has J symbols more storage than the preceding register. The first interleaver path has zero delay, the second has a J symbol period of delay, the third 2*J symbol periods of delay, and so on, up to the Ith path which has (I−1)*J symbol periods of delay. This is reversed for the de-interleaver in the Cable Decoder such that the net delay of each RS symbol is the same through the interleaver and de-interleaver. Burst noise in the channel causes a series of bad symbols. These are spread over many RS blocks by the de-interleaver such that the resultant symbol errors per block are within the range of the RS decoder correction capability.
Related Patents and Publications
Reference is made to ITU-T Recommendation J.83 (Digital multi-program systems for television, sound and data services for cable distribution), Section B.5.2 Page 21 (4/97), hereinafter referred to as “ITU Specification”, incorporated by reference in its entirety herein.
US Patent Publication No. 2005/0063421 (“Wan”), incorporated by reference in its entirety herein, discloses convolutional interleaver and deinterleaver. As disclosed therein, an interleaver or deinterleaver convolutionally interleaves or deinterleaves an incoming word sequence to form an outgoing word sequence. The interleaver or deinterleaver includes an external memory read and write accessed by a direct memory access (DMA) controller for storing bytes forming words of the incoming word sequence until the bytes are needed to form words of the outgoing sequence. The interleaver uses a cache memory to store bytes of a next set of outgoing sequence words. The interleaver initially writes bytes of each incoming word to the external memory and also writes some bytes of the incoming words directly to the cache memory when they are to form parts of the outgoing sequence words currently stored in the cache memory. The interleaver transfers bytes from the main memory to the cache memory when the bytes are needed to form a next set of output sequence words. The deinterleaver stores bytes of incoming words in its cache memory until the cache memory is filled and then DMA transfers them to the external memory. The deinterleaver forms words of the output sequence from bytes it obtains from both its cache memory and its external memory.
Wan discloses a number of Interleavers, more particularly, FIG. 3 of Wan illustrates a prior art interleaver 18 including a controller 28, an input buffer 30, a static random access memory (SRAM) 32 and an output buffer 34 all of which may be implemented on the same integrated circuit (IC) 35. FEC encoder 16 (Wan FIG. 1) writes successive bytes of each successive word of sequence A into input buffer 30, and whenever it has written an entire word of sequence A into buffer 30 it pulses an INPUT_READY input signal to controller 28. Controller 28 responds to the INPUT_READY signal by writing each byte of the sequence A word in buffer 30 to a separate address of SRAM 32. Controller 28 then sequentially reads each byte that is to form a next word of sequence B out of SRAM 32, stores it in output buffer 34 and then sends an OUTPUT_READY signal to modulator 20 (Wan FIG. 1) telling it that it may read a next word of sequence B out of output buffer 34.
The algorithm controller 28 employed for producing read and write addresses for SDRAM 32 ensures that each incoming word of sequence A into SRAM 32 overwrites a previous word of sequence A that is no longer needed and ensures that bytes forming words of sequence B are read in the proper order. To interleave N-byte words of incoming sequence A with an interleaving depth D, SRAM 32 must have D×N addressable byte storage locations. The interleaver architecture illustrated in Wan FIG. 3 is typically employed when interleaver 18 can be implemented on a single IC 35, but when N×D is large it becomes impractical to embed a sufficiently large SDRAM 32 in a single IC.
Wan FIG. 4 illustrates another prior art architecture for an interleaver 18′ including a controller 28′, an input buffer 30′ and an output buffer 34′ included within a single IC 35′. Interleaver 18′ employs an external synchronous dynamic random access memory (SDRAM) 36 for storing bytes rather than an internal SRAM. While controller 28 of Wan FIG. 3 can directly read and write accesses each byte of SRAM 32, controller 28′ of Wan FIG. 4 can only access data in SDRAM 36 via a direct memory access (DMA) controller 38. Rather than individually read and write accessing each byte stored in SDRAM 36, DMA controller 38 operates in a “burst” mode wherein it read or write accesses bytes stored at several (typically 16) successive addresses. Thus when controller 28′ wants to obtain particular bytes stored in SDRAM 36 to write into output buffer 34′, it must ask DMA controller 38 to read a block of bytes including the particular bytes needed to form the next output sequence word. Controller 28′ then transfers those particular bytes to output buffer 34′. However since bytes are not addressed in SDRAM in the order in which they are needed to from bytes of the outgoing word sequence, many of the bytes DMA controller 38 reads from SDRAM 36 during each DMA read access will be discarded.
Since SDRAMs are relatively inexpensive, it can be more cost effective for an interleaver or deinterleaver to employ the architecture of Wan FIG. 4 than that of Wan FIG. 3, particularly when a large amount of memory is needed. However since read and write access to an internal SRAM is typically faster than that of an external SDRAM, interleaver 18 of Wan FIG. 3 can have a higher throughput (in bytes per second) than interleaver 18′ of Wan FIG. 4. The maximum throughput of the interleaver of FIG. 4 can be further limited because much of the bandwidth of SDRAM 36 is wasted reading bytes that are discarded.
Wan FIG. 5 depicts an example of a convolutional interleaver 39 in accordance with the invention including a controller 40, an input buffer 42, a direct memory access (DMA) controller 44, a multiplexer 48, a cache memory 50 and an output buffer 52 all of which are preferably implemented on a single integrated circuit (IC) chip 53. DMA controller 44 read and write accesses a “main” memory 46, suitably an SDRAM external to IC chip 53. Interleaver 39 convolutionally interleaves a sequence A of N-byte incoming words with an interleaving depth D ranging up to Dmax to form a sequence B of N-byte outgoing words. The number N of bytes in each incoming word and in each outgoing word may range up to a maximum number Nmax, such as for example 255. Controller 40 is suitably implemented as a programmable state machine so that the values of N and D can be selected by the manner in which controller 40 is programmed.
Main memory 46 suitably has a least Nmax×Dmax storage locations, with each addressable storage location sized to hold a single byte. DMA controller 44 operates in a burst read and write mode wherein it read or write accesses many successive addresses of main memory 46 whenever it read or write accesses main memory 46. Cache memory 50 preferably includes at least BurstLen×Dmax storage locations where BurstLen is the number (e.g. 16) of successive addresses DMA controller accesses during each burst mode read or write access (its “burst length”). Cache memory 50 can also store one byte at each of its addressable storage locations, but controller 40 can separately and independently read and write access each of its addressable storage locations.
Thus as described above, interleaver 39 uses main memory 46 for storing bytes only when the N×D exceeds the number of available storage locations in cache memory 50 and uses only cache memory 50 for storing bytes of incoming words until they are needed to form outgoing words. Otherwise, interleaver 39 uses main memory 46 for storing all input sequence words and uses cache memory 50 for storing bytes of only as many output sequence words as it can hold.
Cache memory 50 improves the efficiency of DMA read accesses of interleaver 39 compared to the prior art interleaver of Wan FIG. 4 because it reduces the number of bytes its DMA controller reads that have to be discarded. The DMA controller of the prior art interleaver of Wan FIG. 4 reads bytes that are to be included in several outgoing sequence words during each DMA read access, but only those bytes to be incorporated into the next outgoing sequence word are actually used; the rest of the bytes the DMA controller reads are discarded and must be read again at other times when they are actually needed to form a next output sequence word. Since the cache memory 50 of interleaver 39 of Wan FIG. 5 can hold bytes that are to form many outgoing sequence words, fewer of the bytes DMA controller 44 need be discarded. Cache memory 50 therefore reduces the frequency with which DMA controller 44 must read access main memory 46, thereby increasing the interleaver's available throughput.
U.S. Pat. No. 7,051,171 (“Liu”), incorporated by reference in its entirety herein, discloses method and system for providing a multi-channel interleaver/deinterleaver using SDRAM. A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and precharged cycles in order to achieve high data rate operations. The data bus length of the SDRAM is designed to be twice the deinterleaving symbol size thereby allowing bandwidth to be increased. The deinterleaver accesses data in the SDRAM as read blocks and write blocks. Each block includes a predetermined number of data words to be interleaved/deinterleaved. The ACTIVE command for one block is issued when a preceding block is being processed. Data in one read/write block has the same row address within the same bank of the SDRAM. More particularly,
Liu FIG. 2 illustrates a simplified block diagram of a convolutional deinterleaver 21 according to one exemplary embodiment of the present invention. The convolutional deinterleaver 21 is implemented using an SDRAM 22. In this exemplary embodiment, the data or symbol size is eight (8) bits and the word size is sixteen (16) bits. (column 3, lines 16-21)
As shown in Liu FIG. 2, the input buffer 24 combines two symbols in the same branch of the deinterleaver 21 into a word. The delay between two symbols in the same branch is an integer multiple of the deinterleaving depth I. For each word, the input buffer 24 stores the first symbol until the second symbol of the word is received. When a predetermined number of words for one channel are stored in the input buffer 24, such words, collectively a write block as described further below, are forwarded to the SDRAM write buffer 30 for write processing. According to a preferred embodiment, the size of the input buffer 24 is no more than twice the interleaving depth I. A controller 28 generates a periodic address sequence for the incoming data 34 so that symbols s(t) and s(t+n*I) of one channel are combined to form a word, where n is an integer greater than zero (0). In an exemplary embodiment, n is equal to one (1). Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will know and appreciate how to select the appropriate value for n. (column 3, lines 22-40)
Computer Memory, Generally
The present invention relates largely to efficiently and effectively utilizing computer memory, in the exemplary context of achieving certain goals in interleaving data, such as to accommodate forward error correction (FEC) techniques.
Generally speaking, there are two main forms of computer memory—volatile and non-volatile. Non-Volatile Memory (NVM) is computer memory that can retain the stored information even when not powered. Examples of non-volatile memory include read-only memory, flash memory, most types of magnetic computer storage devices (e.g. hard disks, floppy disk drives, and magnetic tape), optical disc drives, and early computer storage methods such as paper tape and punch cards. Non-volatile memory is typically used for the task of secondary storage, or long-term persistent storage. The most widely used form of primary storage today is a volatile form of random access memory (RAM), meaning that when the computer is shut down, anything contained in RAM is lost. Unfortunately most forms of non-volatile memory have limitations which make it unsuitable for use as primary storage. Typically non-volatile memory either costs more or performs worse than volatile random access memory. (By analogy, the simplest form of a NVM memory cell is a simple light switch. Indeed, such a switch can be set to one of two (binary) positions, and “memorize” that position.)
Internally, computer memory is arranged as a matrix of “memory cells” in rows and columns, like the squares on a checkerboard. The entire organization of rows and columns is called an “array.” Each memory cell is used to store one (or more) bit(s) of data which can be retrieved by indicating the data's row and column location.
Memory cells alone would be worthless without some way to get information in and out of them. So the memory cells have a whole support infrastructure of other specialized circuits. These circuits perform functions such as:                Identifying each row and column (row address select and column address select)        Keeping track of the refresh sequence (counter)        Reading and restoring the signal from a cell (sense amplifier)        Telling a cell whether it should take a charge or not (write enable)        
Other functions of the memory controller include a series of tasks that include identifying the type, speed and amount of memory and checking for errors.
A few types of random access memory (RAM) are now briefly discussed, including SRAM, DRAM, SDRAM and DDR SDRAM, as follows:
SRAM: SRAM stands for Static Random Access memory. Basically a SRAM is an array of flip-flops which is addressable. The array can be configured as such that the data comes out in single bit, 4-bit, 8 bit, etc. . . . format. SRAM technology is volatile just like the flip-flop, its basic memory cell. SRAM has the advantage of being quite fast and simple. Because of that it is often used as a memory component in case the total amount of memory can be small. SRAM is often found on microcontroller boards, either on-or off the CPU-chip because for such applications the amount of memory required is small and it would not pay off to build the extra interface circuitry for DRAMs. Another application where often SRAM memory is found is for cache applications, because of the SRAM high memory speed.
DRAM: DRAM stands for Dynamic Random Access Memory. The word ‘dynamic’ indicates that the data is not held in a flip-flop but rather in a storage cell. The ugly thing about a storage cell is that is it leaks. Because of that, data must be read out and re-written each time before the data is lost. This refresh time interval is usually 4 to 64 ms. The good thing about a storage cell is that it requires only one capacitor and one transistor, whereas a flip-flop connected in an array requires 6 transistors. In trench capacitor memory technology, which is used in all modem DRAMs, the cell access transistor is constructed above the capacitor so the space on chip is ultimately minimized. For this reason DRAM technology has a lower cost per bit than SRAM technology. The disadvantage of the extra circuitry required for refreshing is easily offset by the lower price per bit when using large memory sizes. Therefore the working memory of almost all computing equipment consists of DRAM memory. DRAM memory is, just like SRAM memory constructed as an array of memory cells. A major difference between SRAM and DRAM, however, lies in the addressing technique. With a SRAM an address needs to be presented and the chip will respond with presenting the data of the memory cell at the output, or accepting the data at the input and write it into the addressed cell. With DRAM technology this simple approach is impossible since addressing a row of data without rewriting it will destruct all data in the row because of the dynamic nature.
SDRAM: SDRAM stands for Synchronous Dynamic RAM. In a normal asynchronous DRAM, the addressing and data read/write is sequenced by external circuitry (the chipset) which needs to wait between each sequence to allow the DRAM to respond to its signals and output/accept the data. With normal DRAM, however, the only way to guarantee reliable operation is to respect the timing specifications and allow sufficient timing margin. It is clear that this is a simple but not a very efficient approach. In a SDRAM, a clock signal is presented to the DRAM by the control circuitry (the chipset). This allows the DRAM to synchronise its operation to that of the control circuits so it knows what signal is coming exactly when and can also respond with a very precise timing. This approach allows operation at much higher speeds.
DDR SDRAM: DDR SDRAM stands for Double Data Rate Synchronous Dynamic RAM. DDR chips are clocked on both the rising and falling clock edge, effectively doubling the transfer rate.